Circuit arrangement for the presentation of waveforms on viewing screens utilizing raster deflection

ABSTRACT

There is disclosed herein a sample and inexpensive circuit arrangement for presenting waveforms on viewing screens of the cathode ray type having a light spot, due to the electron beam, deflected in a television-like raster. The presentation of waveforms is achieved by means of a device that delivers the value of the differences between adjacent spaced y values in digital form simultaneously with the light spot sweeping over the viewing screen in the x direction. An interpolation means is connected to the device for forming values of equidistant xcoordinates intermediate the spaced adjacent y values such that they are spaced close enough together to provide the desired resolution in the x direction. A comparison circuit is connected to the interpolating means to compare the y values as formed and the pertinent position of the light spot in the y direction. Due to the comparison, a video signal is provided in accordance with logic criteria that makes it possible to present the desired waveform.

United States Patent Bllxt et al. [451 Aug. 22, 1972 [54] CIRCUIT ARRANGEMENT FOR THE .[57] ABSTRACT PRESENTATION OF WAVEFORMS ON VIEWING SCREENS UTILIZING There IS disclosed herein a sample and Inexpensive RASTER DEFLECTION ClI'Cult' arrangement for presenting waveforms on viewing screens of the cathode'ray type havinga light Inventors! Stefan BliXt; 8 Marlin spot, due to the electron beam, deflected in a televidelssona w of Jakobsbefg, sion-like raster. The presentation of waveforms is Sweden achieved by means of a device that delivers the value [73] Assigne; ln'temafioml W Electric of the differences between adjacent spaced y values in pomtion, New York, digital for; simultaneously witltihthe lijght spot sleeping over t e viewing screen in e x irection. in- Flled- 12, 1970 terpolation means is connected to the device for form- [21] Appl. No.: 88,924 ing values of equidistant x-coordinates intermediate the spaced adjacent y values such that they are spaced A, close enough together to provide the desired resolu- [51] Int. Cl 3/14 i i th x di tion A omparison circuit-is con-f [58] Field of Search ..340/324 A, 172.5; 235/197, nected to the interpolating means to compare h y 235/198 values as formed and the pertinent position of the light 56] Refernces Cited spot in they direction. Due to the comparison, a video si nal is provided in accordance with logic criteria UNTED STATES PATENTS th at makes it possible to present the desired 3,406,387 10/1968 Werme ..340/324 A waveform. Y 3,396,377 8/1968 Strout ..340/324 A 2,525,893 10/1950 Gloess ..340/324 A Primary Examiner-John W. Caldwell Assistant Examiner-Marshall M. Curtis Attorney-C. Cornell Rems en, Jr., Walter J. Baum, 12 Claims, 12 Drawing Figures Paul W. Hemminger, Charles L. Johnson, Jr., Philip C a v M. Bolton, Isidore Togut, Edward Goldberg and Menotti J. Lombardi, Jr.

STEP GRAPHIC VLINE MEMORY I U l3 i I s REGISTER rw INPUT 1 W8 -(7 ans) \I/ALUE E 16 N I I Dim. L l RGISTER l6 9 gig? E ADDER VAILUE \ymmm l l 'ADDER A4 1 (10 ans) I 7m, s,g T5 A 1 M i .fwmmsi, OUTPUT REGISTER A5 1 CLOCK (l0 BITS) i L |N rama flfluqwluni L: 10 COMESEIA TQ PU LOG C VIDEOTO I m cmcunK/fima HOR, SYNC. VERTICAL 1| POSITION COUNTER Patented Aug. 22, 1972 6 Sheets-Sheet 1 In venlors 10$ 23 w: 2.x 05 CE N m v mmzoz 0 00 0 00 00 \0 0 00 0 00. 00 262 25 2.

8. STEFAN LIX? DAG MART/N ANDERS ON Wold) Agent hunted Aug. 22, 1972 3,686,662

6 Sheets-Sheet 2 1 UUUUUUHHUUUUUU UUUU UUUUUUU UUU UUUUUU H UQLNHOD'SOd 183A :10 SLNQLNOIJ Invenlors S, STEFAN l/XT 0A6 MART, MDRSON Patented Aug. 22,, 1972 3,686,662

6 Sheets-Sheet s INPUT F I DELAY {\FRAME I um: I MEMORY 2 i 1| ADDITIONAL r I *ss amac I I REGISTER E E"l l' "11L -4 l I e GRAPHIC CONTROL ALPHANUMERIG/ I LiNE MEMORY Fc UNIT um: MEMORY l l I x ll H RESET I 4 ll I ALPHANUMERIC I I SYMBOL GENERATOR i I [I2 cowt sg mfifm I I REFERENCE I PATTERN I I GENERATOR M|XER I L l I VIDEO CATHODE RAY VERT. vmzo mmnm TU E /SYNC DEQSC TESN H G 3 SYSTEM HOR.SYNC.

Inventors s. srtl-wv' Buxr 0M; MARmv ANDERSON Patented Aug. 22, 1972 6 Sheets-Sheet 5 0R GATE FIG.5A FIG.5B F|G.5C F|G.5D FIG.5E FIG.5F

D-TYPE FLIP FLOP EXCLUSIVE NOR GATE GATE GATE

L AmwmS W GISTER I3 M on E D D A INHIBIT VIDEO Inventors 5. STEAN BL/XT DAG MAR Tl ANDERSON By We.

Agent CIRCUIT ARRANGEMENT FOR THE PRESENTATION OF WAVEFORMS ON VIEWING SCREENS UTILIZING RASTER DEFLECTION BACKGROUND OF THE INVENTION This invention relates to cathode ray type viewing screens and more particularly to a circuit arrangement for the presentation of waveforms, each waveform describing a first variable y as a function of a second variable x on viewing screens of the cathode ray type.

In cathode ray tubes, for example, a light spot having an intensity that may be modulated by a video signal is made to simultaneously weep over the screen in two directions at substantially different sweep frequencies so as to form a line raster, as in a'television system, with the two sweep direction coinciding in the positive or negative x directions and the positive or negative y I sociated-with the waveforms.

In presenting graphic information on viewing screens use has previously been made of apparatus based on the principle of direct ray deflection, wherein the electron ray (not lit) of a cathode ray tube'is first deflected to the starting point of the waveform when drawing a waveform, whereupon the lightis lit and made to follow the waveform exactly as if it were drawn with a pen. The deflection is controlled by stepping in -x and y directions, respectively.

Apparatus of the above-mentioned type is also well suited for the presentation of alphanumeric information on viewing screens. However, such apparatus is complicated in its design and function and, therefore, the cost of manufacturing it is high. 1

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit arrangement for the presentation of waveforms on viewing screens with raster deflection.

Another object of the present invention is to provide a circuit arrangement that can be adapted to an alphanumeric display system and that utilizes principles which minimize the amount of information that need be stored to refresh the image on the viewing screen.

In accordance with the broader aspects of the invention, an external device is adapted to deliver in digital form function values (y values) or differences between function values of adjacent spaced points following each other for a number of equidistant x coordinates, in the order of the x values, simultaneously with the light spot sweeping over the screen in the x direction; interpolating means connected to the external .device is adapted to receive the function values or the differences therebetween, the values or differences following each other in time, for forming y values for equidistant x-coordinates, which will lie close enough together to provide the desired resolution in the x direction; and a comparison circuit connected to the interpolating means and adapted to carry out a comparison between the y values as formed and the pertinent position of the light spot in the y direction,

respectively, which latter position is obtained from a counter connected to the raster-forming circuit, whereby a video signal is provided according to a rule which makes it possible to achieve a continuous waveform, such that the light spot is lit if its position in the y direction either concurs with the latesty value or is located between the points of the latest and the closest preceding y value, respectively.

A feature of the present invention is the provision of a circuit arrangement for presenting waveforms, each of the waveforms describing a first variable y as a function of a second variable x, on'a cathode ray type viewing screen comprising first means coupled to the viewing screen to simultaneously sweep a light spot having an intensity that may be modulated by a video signal over the viewing screen in the x and y directions with substantially different sweep frequencies to form a line raster to establish an imaginary coordinate system for the waveforms; second means to provide sequentially in the order of the value of the second variable the digital value of the differences between the values of adjacent spaced ones of the first variable simultaneously with the light spot sweeping over the viewing screen in the x direction; third means coupled to the second means to provide digital values'for the first variable at equidistant x-coordinates intermediate the values of the adjacent spaced ones of the first variable; fourth means coupled to the first means to provide in digital" form the position of the light spot in the y direction; fifth means coupled to the thirdand fourth means to digitally compare the digital output signal of the third and fourth means; and sixth means coupled to the fifth means to provide the video signal in accordance with predetermined logic criteria to intensity modulate the light spot and thereby achieve a continuous waveform on the viewing screen.

BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other features and objects of this invention will become more apparent by reference to following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates an alphanumeric and graphic presentation of waveforms on a viewing screen of a cathode ray type in accordance with theprinciples of the present invention;

FIG. 2 illustrateson an enlarged scale and in detail a portion of the top most waveform of FIG. 1, outlined by block I;

FIG. 3 is a block diagram of a circuit arrangement for presenting graphic and/or alphanumeric information in accordance with the principles of the present invention;

FIG. 4 is a block diagram of one embodiment of the circuit arrangement for graphic presentation in accordance with the principles of the present invention;

FIG. 5A-5F illustrates logic circuit symbols employed in the block diagrams of FIGS. 6 and 7;

FIG. 6 is a block diagram of one form of interpolator 9, comparator 10 and logic circuit 22 of FIG. 4 in ac-. cordance with the principles of the present invention;

and

FIG. 7 is a block diagram of an alternative embodiment that may be incorporated as part of the interpolator of FIG. 4 in accordance with the principles of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates a typical viewing screen containing thereon alphanumeric information and graphic information, when the circuit arrangement of the present invention is utilized, for example, in observing patients in a hospital. The dimension of the rectangle I on the topmost waveform is one square centimeter and an enlarged detailed illustration of this rectangle is contained in FIG. 2. The enlarged detailed view of rectangle I as shown in FIG. 2 will be employed hereinbelow in describing the operation of the circuit arrangement of the present invention.

FIG. 3 illustrates in block diagram form cathode ray tube 23 containing'a viewing screen which under control of deflection system 24 produces a line raster of the television system type for scanning the electron beam across the viewing screen. Information containing both alphanumeric and graphic signals in binary form are applied to the input of frame memory 2 which contains therein a magnetostrictive delay line 1 which is coupled in a loop through shift register 3. This interconnection enables the information to circulate in memory 2 and to be extracted from shift register 3 by the actuation of a clock pulse from the centrally located control unit 4. Alphanumeric information from shift register 3 is coupled to line memory 5 and, hence, through alphanumeric symbol generator 7 under control of control unit 4. The output of generator 7 is coupled to mixer 8 and, hence, to cathode ray tube 23 wherein the alphanumeric display will be presented on the viewing screen.

In accordance with the principles of this invention, the additional hardware for simultaneous graphic presentation on the viewing screen of cathode ray tube 23 is shown in the block B. This additional equipment includes graphic line memory 6, interpolator 9, vertical position counter 11, comparator logic l0, and reference pattern generator 12. The output of comparator logic 10 and generator 12 are coupled to mixer 8 and, hence, to cathode ray tube 23 for presentation of the various waveforms on the viewing screen thereof.

Basically, the additional equipment of the present invention generates a curve by comparing the y-coordinate of the beam of cathode ray tube 23 with the function value corresponding to the x-coordinateof the beam. If they are equal, i.e.,the y-coordinates for the beam and the curve are the same for the same x-coordinate, the beam is turned on since it is pointing right at the desired curve.

The curves are horizontally oriented on the viewing screen, i.e., the independent variable x runs in the direction of the scanning lines produced by system 24. During generation of a curve, the 80 binary characters describing that curve are circulated in memory 6, so that they are available one at a time during every sweep in the x direction. As the beam moves across the screen from left to right, y-coordinates for the whole curve are generated and compared to the vertical position of the beam, which is obtained by counting scanning lines.

Six hundred and forty picture elements are available horizontally across the screen, but only up to 80 points are stored in memory 6. A continuous curve which consists of straight lines connecting the given points and which will fully utilize the available resolution, is

generated in the following way. In each interval between given spaced points, seven new values are obtained by interpolator 9. The interpolator puts out one interpolated value for each clock pulse, i.e., one value for each picture element the beam passes as it passes from left to right across the screen. The output of interpolator 9 is checked against the contents of vertical position counter 11. If coincidence is obtained, the video signal is set to the white level for the next clock cycle. However, the video is turned on also if the beams vertical position is in the interval between the last two function values from interpolator 9. This is done to avoid discontinuities in the curve, which would otherwise occur when the change of the function value from one clockcycle to the next corresponds to more than one vertical raster unit.

The given function values are seven bit binary num bers, corresponding to the integers between 0 and 127,

for example. Interpolator 9 has to work with three bits accomplish this by keeping the number in register 15 one half greater than the true interpolated value.

It should be noted that FIG. 2 is a detail of a complete frame, i.e., both the odd and even fields are shown. Frame memory 2 has a frame time or duration that corresponds to the frame time or duration produced by raster deflection system 24.

In accordance with the present invention, a curve or a waveform is specified by a computer as a string of seven-bit words, or characters, the first one of which is a special code defining the succeeding characters as graphic information. This code may not be used as the first character of an alphanumeric text line. A few characters may be reserved to specify scale factor and coordinate axes, the rest of the 80 characters are used to describe the shape of the curve. Each character, depending on its place in the string, corresponds to a certain character position, horizontally, and the character code is the value of a function in that position; The binary numbers 0100001 (33) through 1111111 (127), a total of different numbers, are allowed as function values. The code 0100000, which is the code for SPACE, can be inserted anywhere in the string or.

stream of characters to turn off the video signal from the comparator logic 10 when scanning across those horizontal positions where no curve is wanted. Numbers less than 32 correspond to control characters and will, therefore, probably not be used in a normal case, although the arrangement of the present invention is fully capable of handling all 128 combinations of seven bits as function values.

The 80 character string is tansferred to and stored in frame memory 2 as one of the text lines. The vertical position of a curve will depend on which one of the lines is chosen. The text capacity will, of course, be reduced by one line for each curve. The video signal from generator 7 has to be blanked out during the time when it would normally generate those text lines whose place in the memory 2 is now occupied by graphic information.

Frame memory 2 consists of a delay line, the ends of which are connected together by shift registers 3. From shift register 3 data is available for the alphanumeric presentation part of the system, and also for block B. The device will read each text line which starts with the special character and circulate that line in its own memory 6 until it reads a line again.

Hence, the line of information intended for graphic presentation on viewing screen of cathode ray tube 23 may be introduced into line memory 6 of the shift register type. The contents of line memory 6 may be circulated in a closed loop fashion. Line memory 6, intended for graphic information, may be of the same type as line memory 5, intended for alphanumeric information, which consists of seven shift registers capable of recirculating the contents therein. Interpolator 9 and comparator logic 10 are connected in series between memory 6 and mixer 8. Vertical position counter 11 is connected between control unit 4 and comparator logic 10. Generator 12 generating a reference pattern, may be positioned between graphic memory 6 and mixer 8.

In the arrangement in accordance with the present invention, an information quantity corresponding only to one line of text is necessary for generating a waveform. This information is read into memory 6 and is retained there until all available levels have been tranversed or until new information may be read into memory 6 from memory 2 with the new information being intended for drawing a new waveform below the first waveform. The information consists of 80 sevenbit characters. One character may be reserved for identifying the pertinent line as graphic information, and furthermore characters may be reserved for specifying scale factors, positions of coordinate axes, and so forth. All the 80 characters may be read out during each horizontal sweep, with memory 6 being indexed by one-eigth of a clock frequency (FC/8) from control unit 4. Those characters in a line that are utilized for describing the waveform proper simply consist of seven-bits binary numbers representing the value of the function in the corresponding horizontal character positions, However, all the 128 combinations of a set of 7 bits can normally not be utilized. The numbers 0 31 are reserved for control characters. In order to interrupt a waveform or to extinguish portions thereof, the number 32 may be appropriately utilized. Normally,

- also the number 127 is excluded. Thus, the function values that may be permitted are 33 126, i.e., a total of 94 values.

The coordinate points described by the information in memory 6 are always clamped to the 80 character positions horizontally and may lie at 94 different levels vertically. By means of the circuit arrangement inaccordance with the present invention, it becomes possible to draw a continuous waveform by interconnecting points by straight lines. These lines are built-up by dots, the positions of which are obtained by interpolating between the given spaced values in the interpolator and by comparison in comparator logic 10 with the values of the vertical position counter 11. The number of possible positions for the latter dots is solely limited by the clock frequency, (horizontally) and the television raster (vertically).

At each eighth clock pulse from control unit 4, a new function value is supplied to interpolator 9 from line memory 6. This number is introduced into register 13 (FIG. 4), which is directly connected to line memory 6. The number occurring at the output of adder 14 in FIG. 4 is simultaneously introduced into the register 15 which is connected to adder 14. However, the three least significant positions, the binals, in register 15 are (at each eighth clock pulse) made equal to binary 100, i.e., one-half, irrespective of adder 14. The seven most significant sum bits from adder 14 are complemented and introduced into registerl6. The circuit is now such that adder 17 ,adds the numbers in registers 13 and 16 and adds an additional 1 (the carry input constant equal one).- The value at the carry output is inverted. I

Adder 17 now provides an eight-bit number which is equal to the difference between the values of register 13 and the integer portion of register 15 (the seven most significant positions). If the difference is negative,

the same is obtained in two's complement form. Adder 14 adds the obtained number to the least significant bits in register 15 (the sign bit of the difference expanded). This means displacement to the right by three positions, i.e., the difference is divided by 8. At the seven nearest following clock pulses only register 15 is set. Its contents are changed each time by one-eighth of the original difference between the value of register 13 and the value of the integer portion of register 15. The

number set in register 15 when the next function value is set in register 13 is equal to one-half plus the integer that was present in register 13 shortly before. Now also the ones complement of this number is set in register 16 and a new difference is calculated.

The integer portion of the value in register 15 is now compared in comparator logic 10 to the contents of the vertical position counter 11 which is assumed to count downwards from 127. It is not sufficient to determine whether equality exists, if gaps in the waveform cannot be tolerated, when the difference between two function values following each other exceeds 8. Two signals a and b are formed in such a manner that a l when the value of counter 11 is greater than the value of register 15, other a =O. b 1 if the value of counter 11 is equal to the value of register 15, otherwise b 0. At each clock pulse signals a and b are stored in two flip-flop circuits 20 and 21. In addition to signals a and b, signal c, which is equal to the previous value of a, and signal d, which is equal to the previous value of b now occur. With the aid of signals a, b, c and d logic circuit 22 provides the ultimate video output signal which is equal to l corresponding to white, if the value in counter 11 is equal to the value in register 15 or if the value in counter 11 is greater than the value in register 15 but smaller than the previous value in register 15 or if the value in counter 11 is smaller than the value in register 15, but greater than the previous value in register 15, otherwise, the video signal is equal to 0, corresponding to black.

With the prototype circuit, the vertical unit of length can be changed from one to two TV scan lines. Then the comparison must be carried out with 8 bits instead of with 7 bits from vertical counter 11, as the thickness of the waveform will be doubled otherwise, measured vertically. The additional bit is added to the left of (i.e., is less significant than) the 7 bits that normally are compared to the integer portion of the value in register 15. For circuit economy reasons, the comparison is carried out with the corresponding additional bit in register 15 being assumed to be equal to l. In order to improve the shape of the video signal an additional flip flop circuit is utilized (see flip flop 25 of logic circuit 22 of FIG. 6). (In the illustration-of FIG. 2 consideration has not been given to the delay introduced by the flip flop, which will shift the image one step to the right with respect to the table of the contents of register 15).

The operation of the circuit of FIGS. 3, 4 and 6 may be more fully appreciated by referring to FIG. 2 which shows an enlarged view of the small area I of the viewing screen as illustrated in FIG. 1. The width of the area correspond to 33 clock cycles (four character positions). The numbers at the bottom of FIG. 2 show the contents of register 15 in each of the 33 cycles. The

. same numbers will be obtained in these horizontal positions for each line sweep. The number 26 is set in register'13 8 cycles before the first cycle shown. During the first cycle, register 15 will, therefore, contain 26%. At the same time that this number is put into register 15, a new function value is received from memory 6 by register 13. The new value is equal to 6. The difference, 6 26 ==20 is calculated. Division by 8 results in 2%. At the next clock pulse this number will be added to the contents of register 15, so that this register will in the second cycle, contain 26%: 2%= 24. In the third cycle the number in register 15 will be 24 2%= 21% and so on. The number =2% will not change until registers 13 and 16 are set again, which is at the start of the ninth cycle shown. At this time, the contents of register 15 will be 6%, the number 6 is put into register 16 and register 13 gets the new function value 3 from memory 6. The increment, which was previously =2%, will now change to (3 6)l8 3/8, so that register 15 will contain 6% 3/8 =6 1/8 in the tenth cycle, 6 H8 3/8 =5 6/8 in the 1 1th cycle and so forth. The next two values in line memory 6 are 4 and 19. They are put into register 13 at the start of the 17th and 25th cycle, and appear in the integer part of register 15 during the 25th and the 33rd cycle, respectively.

FIG. 5A illustrates the symbol for a D-type flip flop.

FIG. 53 illustrates the symbol employed for a binary full adder wherein the inputs to A and B are to be summed with the sum output S being provided on one output and the complement of the sum S being provided on the other output. is the carry input and C,- is the complen r ent of the carry input while C is the carry output and C is the complement of the carry output.

FIG. C illustrates the symbol for a NOR gate.

FIG. 5D is the symbol for an EXCLUSIVE NOR gate.

FIG. SE is the symbol for an inverter or a NOT gate.

FIG. 5 F is a symbol for an OR gate.

The symbols of FIG. 5A to FIG. 5F will be employed in the schematic block diagrams of FIGS. 6 and 7 to be discussed hereinbelow.

Referring to FIG. 6, there is illustrated therein a schematic diagram in block form, employing the logic symbols of FIG. 5A to FIG. 5F, illustrating the logic circuitry of interpolator 9, comparator logic l0, flip flops 20 and 21, and logic circuit 22. Register 13 includes seven D-type flip flops having their inputs D coupled to the associated stage of memory 6 and their output 0 coupled to the B input of the associated stage of adder 17. Register 16 includes seven D-type flip flops with the output Q being coupled to the A input of the associated full adder of adder l7. Adder 14 includes ten stages of full adders with the seven most significant stages having the S output coupled to the input D of the D-type flip flop stages of register 16. Register 15 includes ten stages of D-type flipflops with the input to the seven most significant stages being coupled to the S output of the seven most significant stages of adder 14 while the three least significant stages of register 15 are coupled to NOT gate 29 and NOR gates 27 and 28 as illustrated. Outputs of the last three full adder stages of adder 14' are coupled to the three corresponding inputs of register 15 through the NOR- gates 26, 27 and 28 and NOT gate 29, which are controlled by a signal from the control unit in such a way that the most significant one of the three inputs is 1" and the other 0 during 1 cycle out of every 8 of a 12.5 MHz clock. Registers 15, 13 and 16 are set at the end'of each one of these cycles. During the other 7 out of every 8 clock cycles, the inputs of the three least significant stages of register 15 are equal to the corresponding S outputs of the three least significant stages of adder 14. Only register 15 is set at the end of each one of these 7 out of 8 cycles. The A input of the 7 least significant stages of adder 14 are derived from the S output of adder 17. The A input for the three most significant stages of adder 14 are provided by the G output of the most significant stage of adder l5.'The B input of each stage of adder 14 is provided from the corresponding stage of register 15.

A number L, representing the beam vertical position, is obtained from vertical position counter 11. Counter 11 is reset each time the line memory 6 receives data from frame memory 2. Presentation of the curve begins as soon as the loading'of memory 6 is completed and counter 11 then starts counting the horizontal sync pulses from control unit 4, the same pulses that are used to synchronize raster deflection system 24. The number L is equal to 127 during the first line sweep after the start of presentation If the scale factor is one, L decreases by one for each TV line. If L reaches zero, i.e., if no other curve is found in frame memory 2 within 128 line sweeps from the start of presentation, counter 11 is disabled until memory 6 receives data again. This is to prevent repetition, within the same field, of the curve just generated.

The number L, as defined above, is used as the vertical reference for comparator logic 10. Operation of this circuitry is best illustrated by the schematic logic diagram of FIG. 6. EXCLUSIVE NOR gates 30-36 compare the number L with the 7 most significant bits stored in register 15. If the most significant bit of L is binary l, and the most significant bit of register 15 is binary 0, or if they are equal, and the second most significant bit of L is 1" and the corresponding bit of register 15 is O, or if these also are equal and the third most significant bit of L is l and the corresponding bit of register 15 is 0, etc. then the logic state will be l at the point which connects the outputs of the seven NOR gates 37 to 43 together. The state at this point is called a. It will be l only if L is greater than the number stored in the most significant stages of register 15. It would be possible to replace the EXCLUSIVE NOR gates by AND gates without affecting the variable a. However, in the logic family of equipment employed the AND function is almost as expensive as the EXCLUSIVE NOR, and the latter is more economic in this arrangement, since the gate simplifies the necessary test for equality of the L and U numbers, the U number being the output of register 15. The EXCLUSIVE NOR gates thus serve two purposes in the circuit. The first purpose is that outlined above and the second purpose is that their outputs are combined in NOR gates 44 to 46 to generate the variable b, which is 1 if and only if L is equal to U.

The two logic variables a and b now contain full information on whether the y-coordinate of the scanning spot is less than, equal to, or greater than the contents of register 15,.which represents the function value corresponding to the x coordinate of the spot. Two D-type flip flops 21 and 20 are used to store functions a and h during the following clock cycle. The output signals of flip flops 21 and 20, c and d, thus contain information on whether the y-coordinate of the spot is less than, equal to, or greater than the function value obtained during the preceding cycle. The signals a, b, c and d are now combined by NOT gates 47 and 48' NOR gates 49-51 to form the video signal. This signal will be logic 1 if and only if the vertical position L of the spot is either equal to the latest function value or less than one of the two latest function values and greater than the other. i

The purpose of flip flop 25 at the output of NOR gate 51 is to improve the shape of the video signal. It will also cause a delay of the signal by one clock cycle as mentioned hereinabove.

Normally, the curve data will be transferred to the frame memory 2 from a computer. It is possible to let the computer take over part of the work done by the equipment of interpolator 9 without increasing the amount of data transmitted by the computer. The

limitations of the system will be somewhat changed, but it depends on the application whether this change is an advantage or a disadvantage. It is clear, however, that parts count and manufacturing costs of the arrangement will be reduced, and the increase of the computer workload will be small.

The work that can be handled by the computer is the first step of the interpolation process performed by interpolator 9, i.e., the subtraction. The computer would send the differences between successive function values, instead. of the values themselves. In the block diagram of FIG. 4, register 16 and adder 17 would no longer be needed. Register 13 would contain the difference which is now produced by adder l7 and register 16. The output from register 13 would be connected directly to adder 14. Then the integer part at the output of register will have to be set to a certain initial value at the start of each line sweep. (This could be combined with the setting of one-half into the fraction part of the contents of register 15. It is not necessary to do that for every value received from line memory 6, as is now done).

In the arrangement of FIG. 4, the vertical resolution is limited to 95 levels, if the control characters are not used. In the simplified version, the resolution is not limited by the code employed. Thus, the full capacity of 128 levels can be used (and could easily be increased to 256). However, the difference between the function value and two successive character positions will be restricted to be one of 95 different numbers, 47

through +47. The maximum slope of the curve will, therefore, be one-half of that in the system of FIG. 4.

The increased vertical resolution, as compared with the system of FIG. 4 is thus associated with a further reduction of redundancy, namely, that redundancy which is due to the correlation between consecutive values of a not rapidly changing function.

The characters that are received from memory 13 have to be transformed before being applied to adder 14. The numbers -47 to 1 are in memory 6 represented by the codes 0100001 to 100111, and these should be changed to 1010001 to 111 l l l l. The numbers 0 to +47 are represented by 1010000 to 1111111, which should be transformed to 000000 to 0101111. The code 010000, representing SPACE, should be changed to 0000000, otherwise it will be difficult to use SPACE to the left of a curve. FIG. 7 illustrates the logic circuitry including NOR gates 5257 be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof an in the accompanying claims.

We claim:

l. A circuit arrangement for presenting waveforms, each of said waveforms describing a first variable y as a function of a second variable x, each of said first and second variables being represented by a plurality of spaced points, each of said spaced points of an associated one of said first and second variables having a difference value, on a cathode ray type viewing screen comprising:

first means coupled to said viewing screen to simultaneously sweep a light spot having an intensity that may be modulated by a video signal over said viewing screen in the x and y directions with substantially different sweep frequencies to form a line raster to establish an imaginary coordinate system for said waveform;

second means to provide sequentially in the order of the values of said second variable the digital value of the differences between the values of adjacent ones of said spaced points of said first variable simultaneously with said light spot sweeping over said viewing screen in said x direction;

third means including digital arithmetic means coupled to said second means to provide digital values for said first variable atequidistant x-coordinates intermediate said values of said adjacent ones of said spaced points of said first variable;

fourth means coupled to said first means to provide in digital form the position of said light spot on said viewing screen in said y direction;

fifth means coupled to said third and fourth means to digitally compare the digital output signals of said third and fourth means; and

sixth means coupled to said fifth means to provide second logic circuitry coupled to said first logic cirsaid video signal in the form of either of two binary cuitry to provide said video signal. levels in accordance with predetermined logic criteria to intensity modulate said light spot and wherein said third means further includes thereby present a waveform on said viewing 7. A circuit arrangement according to claim 6,

an adder having N n stages coupled between said Screensecond means and said register,

cil'cuit arrangement according to claim each of the n most significant stages of said adder r u receiving the most significant bit of said digital 531d vldeo $181131 Provided by Said Sixth means causes 1 0 value of said difference between the values of said said light spot to be lit when said output signal of said fourth means equals said output signal of said third means and when said output signal of said forth means is greater than said output signal of said third means for the latest value of said first adjacent ones of said spaced points of said. first variable and each of the remaining N stages of said adder receiving a different one of the remaining bits of said digital value of said difference between a 15 the values of said adjacent ones of said spaced variable but less than said output signal of said points ofsaid first variable and h means the immediately Preceding value each of the N n stages of said adder being coupled of vanable' to a different one of the N n, stages of said re f clrcmt arrangement according to clalm gister to enable coupling digital values in two. wherem directions between said register and said adder;

the faster of said different sweep frequencies defines the horizontal positions of said line raster and occurs in said x direction; and

said second means provides said digital valueof the differences between the values of adjacent ones of said spaced points of said first variable between given levels in said y direction for presentation of one waveform and other different digital values of the differences between the values of adjacent ones of said spaced points of said first variable between other different levels in said y direction for presentation of other waveforms.

4. A circuit arrangement according to claim 1,

wherein said third means provide said intermediate digital values for said first variable 2 times more often than said second means provides said digital value of the differences between the values of said adjacent ones of said spaced points of said first varia- 4O ble by accumulative addition of successive ones of said digital value of the difference between the values of said adjacent ones of said spaced points of said first variable, where n is an integer greater than zero. 4

5. A circuit arrangement according to claim 1,

wherein said first means includes seventh means to produce a horizontal sync signal at Second. shlit reglsters' the start of each horizontal line of said line raster; 9 arrangemfmt according to clam and said fourth means includes wherem Sam-Second. means mcludes i v a digital counter coupled to said seventh means to memory means to provlde the value of the count said horizontal sync signal to provide in digital form the position of said light spot on said viewing screen in said Y direction.

6. A circuit arrangement according to claim 1,

wherein said third means includes a register having N +n stages, where n is an integer greater than zero and N is the number of bits in stored dlgltal Value, i said digital values of the difference between the an adder couplefl to f memory means f 531d values f Said adjacent ones f Said spaced points means to obtain the digital value of the difference of said first variables; said fourth means includes between the digital Valufi of Said P one of a digital counter having at least M stages, where M is Said adjacent (mes of Said spaced Points of Said a integer less than the sum of M. stages integer first variable and the digital value of said previous values of N and n; said fifth means includes one of corrected said adjacent ones of said spaced first logic circuitry coupled to the M most significant points of said first variable.

stages of said register and the M stages of said 11. A circuit arrangement according to claim 1, digital counter; and said sixth means includes wherein said second means includes 8. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the points of said first variable, a first register coupled to said third means to store one of said adjacent ones. of said spaced points of 30 said first variable, and I i an adder coupled to said memory means and said first register to obtain the digital value of the dif-, ference between the digital value of said present one of said adjacent ones of said spaced points of 35 said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable. 9. A circuit arrangement according to claim 8, wherein said memory means includes N second shift registers, where N is the number of bits in said digital values of said adjacent ones of said second shift registers including logic circuitry to circulate therein the contents thereof, and

a third shift register having N inputs, each of said N inputs being coupled to a different one of said points of said first variable,

a register coupled to said third means to store the digital value of the previous one of said adjacent ones of said spaced points of said first variable,

means coupled to said register to complement said present one of said adjacent ones of said spaced the complement of the digital value of the previoussaid spaced points of said first variable, each of present one of said adjacent ones of said spaced 13 14 memory means to provide the digital value of the first variable and the digital value of said previous present and previous ones of said adjacent ones of one of said adjacent ones of said spaced points of 7 said spaced points of said first variable, said first variable. a a register coupled to said memory means to store the 12. A circuit arrangement according to claim 1,

digital value of the previous one of said adjacent wher in Sai Sec nd mean incl des ones of said spaced points of said first variable, memory means to provide the digital value of the difmeans coupled to said register to complement said ferences between gi v l e f S i present t d digit l l a d one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.

an adder coupled to said memory means and said means to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said 

1. A circuit arrangement for presenting waveforms, each of said waveforms describing a first variable y as a function of a second variable x, each of said first and second variables being represented by a plurality of spaced points, each of said spaced points of an associated one of said first and second variables having a difference value, on a cathode ray type viewing screen comprising: first means coupled to said viewing screen to simultaneously sweep a light spot having an intensity that may be modulated by a video signal over said viewing screen in the x and y directions with substantially different sweep frequencies to form a line raster to establish an imaginary coordinAte system for said waveform; second means to provide sequentially in the order of the values of said second variable the digital value of the differences between the values of adjacent ones of said spaced points of said first variable simultaneously with said light spot sweeping over said viewing screen in said x direction; third means including digital arithmetic means coupled to said second means to provide digital values for said first variable at equidistant x-coordinates intermediate said values of said adjacent ones of said spaced points of said first variable; fourth means coupled to said first means to provide in digital form the position of said light spot on said viewing screen in said y direction; fifth means coupled to said third and fourth means to digitally compare the digital output signals of said third and fourth means; and sixth means coupled to said fifth means to provide said video signal in the form of either of two binary levels in accordance with predetermined logic criteria to intensity modulate said light spot and thereby present a waveform on said viewing screen.
 2. A circuit arrangement according to claim 1, wherein said video signal provided by said sixth means causes said light spot to be lit when said output signal of said fourth means equals said output signal of said third means and when said output signal of said forth means is greater than said output signal of said third means for the latest value of said first variable but less than said output signal of said third means for the immediately preceding value of said first variable.
 3. A circuit arrangement according to claim 1, wherein the faster of said different sweep frequencies defines the horizontal positions of said line raster and occurs in said x direction; and said second means provides said digital value of the differences between the values of adjacent ones of said spaced points of said first variable between given levels in said y direction for presentation of one waveform and other different digital values of the differences between the values of adjacent ones of said spaced points of said first variable between other different levels in said y direction for presentation of other waveforms.
 4. A circuit arrangement according to claim 1, wherein said third means provide said intermediate digital values for said first variable 2n times more often than said second means provides said digital value of the differences between the values of said adjacent ones of said spaced points of said first variable by accumulative addition of successive ones of said digital value of the difference between the values of said adjacent ones of said spaced points of said first variable, where n is an integer greater than zero.
 5. A circuit arrangement according to claim 1, wherein said first means includes seventh means to produce a horizontal sync signal at the start of each horizontal line of said line raster; and said fourth means includes a digital counter coupled to said seventh means to count said horizontal sync signal to provide in digital form the position of said light spot on said viewing screen in said y direction.
 6. A circuit arrangement according to claim 1, wherein said third means includes a register having N +n stages, where n is an integer greater than zero and N is the number of bits in said digital values of the difference between the values of said adjacent ones of said spaced points of said first variables; said fourth means includes a digital counter having at least M stages, where M is a integer less than the sum of the integer values of N and n; said fifth means includes first logic circuitry coupled to the M most significant stages of said register and the M stages of said digital counter; and said sixth means includes second logic circuitry coupled to said first logic circuitry to provide said video signal.
 7. A circuit arrangement according to claim 6, wherein said third means further includes an adder having N + n stages coupled between said second means and said register, each of the n most significant stages of said adder receiving the most significant bit of said digital value of said difference between the values of said adjacent ones of said spaced points of said first variable and each of the remaining N stages of said adder receiving a different one of the remaining bits of said digital value of said difference between the values of said adjacent ones of said spaced points of said first variable, and each of the N + n stages of said adder being coupled to a different one of the N + n stages of said register to enable coupling digital values in two directions between said register and said adder.
 8. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present one of said adjacent ones of said spaced points of said first variable, a first register coupled to said third means to store the complement of the digital value of the previous one of said adjacent ones of said spaced points of said first variable, and an adder coupled to said memory means and said first register to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.
 9. A circuit arrangement according to claim 8, wherein said memory means includes N second shift registers, where N is the number of bits in said digital values of said adjacent ones of said spaced points of said first variable, each of said second shift registers including logic circuitry to circulate therein the contents thereof, and a third shift register having N inputs, each of said N inputs being coupled to a different one of said second shift registers.
 10. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present one of said adjacent ones of said spaced points of said first variable, a register coupled to said third means to store the digital value of the previous one of said adjacent ones of said spaced points of said first variable, means coupled to said register to complement said stored digital value, and an adder coupled to said memory means and said means to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.
 11. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present and previous ones of said adjacent ones of said spaced points of said first variable, a register coupled to said memory means to store the digital value of the previous one of said adjacent ones of said spaced points of said first variable, means coupled to said register to complement said stored digital value, and an adder coupled to said memory means and said means to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.
 12. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the differences between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced poinTs of said first variable. 